As known in the art, through-substrate vias (referred to herein as TSVs), which are commonly referred to as through-silicon vias, are vertical electrical connections that extend from one of the electrically conductive levels formed on the top side of the IC die (e.g., one of the metal interconnect levels) to the bottom side of the IC die. TSVs are commonly used as power TSVs (e.g., for VDD, VSS or ground) and/or signal TSVs.
TSVs allow the TSV comprising IC to be bonded to on both sides and utilize vertical electrical paths to couple to other IC devices (in either singulated die or wafer form), or to mount either side to a package substrate or interposer. The vertical electrical paths are significantly shortened relative to conventional wire bonding technology, generally leading to significantly faster device operation of the IC.
TSVs can be formed in a “via-first,” a “via-middle,” or a “via-last” approach. In the via-first approach the TSVs are formed in the wafer fab during front end processing. Via-first generally comprises TSV formation before the transistors (e.g. CMOS and/or bipolar transistors) are formed, and due to high temperature transistor processing (e.g. >900° C.), low resistivity metals which are not high temperature tolerant, such as copper, cannot be used as a TSV conductor. A via-middle approach generally takes place after transistor formation but before passivation processing, such as between the contact level and first metal interconnect, or after one or more levels of metal interconnect. For via-middle TSV processes, the TSVs after chemical-mechanical polishing (CMP) are next subjected to moderate temperature processing to form the dielectric over the TSVs, such as around 300 to 400° C. The via-last approach takes place in assembly and packaging and typically forms the TSVs from the bottom side of the IC die after wafer fab processing is completed (i.e. after passivation processing), so that via-last TSVs are generally not exposed to moderate temperature processing.